Vhdl code muxdemux.vhdl. Using VHDL-2008 it can be done like. Thanks for the MUX, it works fine and is a very short and clear code. I have problems with the DEMUX now, using the same.
It has 3 inputs: 1-bit sel (selector), 4-bit X[3.0] and 4-bit Y[3.0]. It uses two 4to2 Multiplexer blocks (4to2MUX). It has one 4-bit output m[3.0].
-- 8 to 4 Multiplexer
-- inputs: 1-bit sel (selector), 4-bit X, 4-bit Y
-- outputs: 4-bit m
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity MUX8_4 is
PORT( sel: in bit;
X, Y: in bit_vector(3 downto 0);
m: out bit_vector(3 downto 0));
end MUX8_4;
architecture logic of MUX8_4 is
component MUX4_2 is
PORT( sel, X0, X1, Y0, Y1: in bit;
m0, m1: out bit);
end component;
begin
mux4_2_inst0 : MUX4_2
PORT MAP( sel => sel, X0 => X(0), X1 => X(1), Y0 => Y(0), Y1 => Y(1),
m0 => m(0), m1 => m(1));
mux4_2_inst1 : MUX4_2
PORT MAP( sel => sel, X0 => X(2), X1 => X(3), Y0 => Y(2), Y1 => Y(3),
m0 => m(2), m1 => m(3));
end logic;
-- inputs: 1-bit sel (selector), 4-bit X, 4-bit Y
-- outputs: 4-bit m
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity MUX8_4 is
PORT( sel: in bit;
X, Y: in bit_vector(3 downto 0);
m: out bit_vector(3 downto 0));
end MUX8_4;
architecture logic of MUX8_4 is
component MUX4_2 is
PORT( sel, X0, X1, Y0, Y1: in bit;
m0, m1: out bit);
end component;
begin
mux4_2_inst0 : MUX4_2
PORT MAP( sel => sel, X0 => X(0), X1 => X(1), Y0 => Y(0), Y1 => Y(1),
m0 => m(0), m1 => m(1));
mux4_2_inst1 : MUX4_2
PORT MAP( sel => sel, X0 => X(2), X1 => X(3), Y0 => Y(2), Y1 => Y(3),
m0 => m(2), m1 => m(3));
end logic;
1*16 Demux Vhdl Code
1X8 DEMUX VHDL source code
Wii theme song violin sheet music. This page of VHDL source code covers 1X8 DEMUX vhdl code.
VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dmux1 is
port(f:in std_logic;
s:in std_logic_vector(2 downto 0);
y:out std_logic_vector(7 downto 0));
end demux1;
architectural behavioral of dmux1 is
begin
y(0)<=f when s='000'else'0';
y(1)<=f when s='001'else'0';
y(2)<=f when s='010'else'0';
y(3)<=f when s='011'else'0';
y(4)<=f when s='100'else'0';
y(5)<=f when s='101'else'0';
y(6)<=f when s='110'else'0';
y(7)<=f when s='111'else'0';
end behavioral;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dmux1 is
port(f:in std_logic;
s:in std_logic_vector(2 downto 0);
y:out std_logic_vector(7 downto 0));
end demux1;
architectural behavioral of dmux1 is
begin
y(0)<=f when s='000'else'0';
y(1)<=f when s='001'else'0';
y(2)<=f when s='010'else'0';
y(3)<=f when s='011'else'0';
y(4)<=f when s='100'else'0';
y(5)<=f when s='101'else'0';
y(6)<=f when s='110'else'0';
y(7)<=f when s='111'else'0';
end behavioral;
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